Aims of the project and objectives

                The aim of this project is to fabricate a working S-R flip-flops using nMOS processing which will be adapted from the UMIST pMOS process. To achieve this aim several objectives are determined and listed as follows:

                -Fabrication of S-R flip-flop from existing masks.

                -Testing the device including the test capacitor.

                -Modelling the oxide capacitor and p-MOS transistor.

                -Simulating the device, with calculated values, on a PC.

                -Estimation of n-MOS characteristics to achieve maximum performance in the final stage.

                -Modelling oxide capacitor and n-MOS transistor.

                -Simulation of the capacitor and n-MOS devices on a PC.

                -Adding up the results, and deciding on the changes to be made for n-MOS.

                -Fabrication of the S-R flip-flop from existing masks with calculated values.  (P substrate n-MOS version)

                -Testing the device

                -Comparing the results and investigation of the future improvements.



S-R flip-flop:

Flip-flops are the basics of digital data storage devices. Although these devices are mostly volatile, they provide simplicity in usage and cost/performance efficiency. Basic schematics of an S-R flip-flop and its truth table is as follows:





MOSFET, metal oxide silicon field effect transistor, is the most commonly used FET device. FET devices differ from bipolar transistor in the way they operate, because they are:

                -Voltage controlled


                                Holes:       in a p-channel FET

                                Electrons: in an n-channel FET

MOSFET can be thought as a sandwich consisting of a thin layer of “filling” made of very pure SiO2 placed between two conducting plates.





an n-MOS device structure









A p-MOS enhancement transistor


A nand gate (p-MOS version)



An n-MOS enhancement transistor




MOSFET capacitance:

The dynamic response (e.g. switching speed) of MOS systems are strongly dependent on the parasitic capacitances associated with MOS device and interconnection capacitances that are formed by metal wires in concert with transistor and conductor resistances. The total capacitance on the output of a MOS gate is the sum of:

                -Gate capacitance

                -Diffusion capacitance

                -Depletion layer capacitance

 Diagram of capacitances according to surface mode (p substrate)






Channel is the inversion layer where the MOSFET is on.



                Apart from fabrication of the first p-MOS and final n-MOS device, whole project builds on the careful study of the MOSFET capacitor. This capacitor with a dielectric layer consisting of a high purity SiO2 determines the delay time of each transistor hence NAND gate.

                This delay consists of tr, tf, td:

                tr: rise time 10% to 90% of its steady state value

                tf: fall time 90% to 10% of its steady state value

                Td: time difference between 50% of input transition to 50% of output transition (logic transition)

                To give a rough idea of rise and fall times, if we assume tf is the fall time for a CMOS device which consists of equally sized p-MOS and n-MOS transistors,  tr=2*tf     and   td= tr/2.

                These three values are mostly dependent on capacitor and mobility.

                So we can sum up our strategy as follows:

                -A theoretical work of MOSFET speed and capacitance values will be studied.

                -By using the test capacitor on the silicon chip, a set values to be used in the simulation will be extracted.

                -Extracted and rounded values will be used to achieve a SPICE model of the same capacitor.

                -Modelling and comparing the fabricated p-MOS using SPICE model.

                After this stage, we can reverse the procedure for n-MOS values and get an estimated model of the actual device. By considering the limitations that we will discover from the p-MOS fabrication, an optimised model and a corresponding device will be fabricated.



                As stated above. First and the last phases of the project aims to fabricate p-MOS and n-MOS S-R flip-flops. All the following steps, depends on the first step. To get a good, working device one must know and obey the clean room rules and procedures. Initially these can be grouped as follows:

                -General Clean Room procedures

                -Safety procedures

                -Fabricating procedures


General Procedures: These procedures involve the special clothing equipment while working in the clean room.


Safety Procedures: There are several safety precautions for the clean room. These procedures are divided in to 3.


Hazardous Chemicals: Device fabrication is highly dependent on dangerous chemicals. These chemicals are mostly acids, organic and flammables.

                 Acids are HF, H2SO4

                         Organic substances are phototoresists.

                Flammables are acetone, ethanol etc.


                Various safety procedures and precautions are included at the end of this report.


Working Procedures: At no time, must one stay alone in the room. There must be always someone at a shout length distance. Also, after finished with the chemicals, disposal and cleaning of the various things must be strictly done according to the instructions.


Electrical Procedures and Furnace: Oxidation process depends on the high temperature (1200C) of the furnace. While using furnace, quartz trays and supplied objects must be used. Temperatures must carefully set and after use, they must be resettled to their initial values. Also possible ignition and spark spreading devices must not be used near flammable gases.


Fabricating Process: Generally this set of procedures can be illustrated as follows:























            Specifically to this project, fabrication cycle takes 24 hours. And this cycle consists of the following procedures:

            1) Cleaning and oxidation of silicon (Thick/wet oxide)

            2) Photoresist, Mask 1, developing, etching.

            3) Photoresist, Mask 2, developing, etching.

            4) Photoresist, Mask 3, developing, etching.

            5) Photoresist, Mask 4, metal coating, etching

            6) Packaging and bonding the die to the package.


            Schematics of the masks are attached at the back of the report.



                Testing procedure involves Hewlett-Packard 4140b pa meter/dc voltage measurement equipment. This equipment is highly sensitive and powerful enough to measure the dynamic characteristics of the oxide capacitor. Through testing, the following points will be clarified:

                -The oxide capacitor values will be measured. Through this measured values, a rough thickness of gate oxide will be calculated.

                -Transistor voltages and working specifications will be graphed.             

                -The flip-flop will be tested.


                Testing procedure is essential for verifying the fabricated chips and getting the mathematical values for later use in the simulations.

Tools and Costs:


                Spice:  Before and after the fabrication, we will need a model of a mathematical model of the capacitor and the transistors. Spice is a freeware tool to simulate electronic components.

Spice has various MOSFET models to help the end user.

Spice is freely available.


                Mathematica: Most of the semiconductor equations are complicated. The constants are extremely large or small. All these factors make understanding the equations very difficult. So to visualise the equations and their correlation with different variables easily, Mathematica is an excellent tool to use. Also with Mathematica, the models of the transistors will be expressed mathematically.


             Semiconductor fabrication:

            Estimation of the Cost Expenditure



lab services (air filtration , etc.)


de-ionized water




paper towels/ lint-free wipes


disposable gloves


safety gear (rubber gloves , etc.)


cleanroom garments


mask making materials


lamps (mask aligner u.v. / microscope)


evaporation materials(tungsten/aluminium)


sputter materials (quartz crystal/targets)


dual-in-line /ceramic bonding packages




photoresist developer




hydrofluoric acid


chromium trioxide


hydrochloric acid


hydrogen peroxide


ammonia fluoride


sulphuric acid


aluminium etch


diffusion sources








Total Cost









This project is divided into 4 phases:





Phase 1

p-MOS R-S flip-flop fabrication and tests

3 weeks

Phase 2

Analysing the test data, theoretical work and changes

4 weeks

Phase 3

n-MOS R-S flip-flop fabrication and tests

3 weeks

Phase 4

Writing an comparing results and further suggestions

3 weeks


Phase 1: The fabrication process takes 24 hours in total. This time will be shared among the 3-week period.

                                Fabrication                                            2-2.5 weeks

                                Testing                                                  1-0.5 week


Phase 2: During this phase various software tools will be used to get an understanding of the characteristic properties of the components. Afterwards they will be modelled and simulated on a PC.


                                Analysing the data                                                                                          1 week

                                Simulating the fabricated components using SPICE                  2 weeks

                                Comparing the results and listing deviations                              0.5 weeks

                                Simulating the n-MOS R-S flip-flop with different parameters    1.5 weeks


Phase 3: This is another 24-hour process. But this phase is given a slightly longer period to ensure that the final device works and meets the simulated model.


                                Fabrication                                                            2 weeks

                                Risk week                                                              1 week


Phase 4: This is a complete 3 week period for analysing the data, making comparisons and investigating further improvements.


                                Deciding outlines of the chapters     0.5 week

                                Writing and finalising                                         2.5 weeks


Total: 13 weeks. 3 weeks are left for general delays.

So expected project length 16 weeks.